SCI Activities in the Manchester HEP Group
From 1992 to 1998 the SCI work in the HEP Group in the Department of Physics and Astronomy at the University of Manchester focused on the Triggering and Data Acquisition needs of high energy particle physics experiments. The group is working on the ATLAS experiment for the LHC accelerator to be built at CERN Geneva. The Manchester HEP group designed and built several interfaces to test the SCI memory-memory interconnect for use in the Level2 Trigger of the ATLAS experiment. SCI was extensively tested at CERN in the ATLAS Demo_B project during 1997 and 1998.
Projects
- SCI daughter Card using the Dolphin NodeChip
- SCI-VME interface
- SCI-C40 interface based on LSI DBV42/44 board
- Custom C40 VME board and SCI interface - Joint with Royal Holloway
- SCI-PCI interface
- ATLAS Level 2 trigger Lab tests and Beam Tests in 1994 and 1995
- RD24 Project at CERN
- SCI Data Generators
Conference Papers
"SCI with DSPs and RISC Processors for LHC 2nd Level Triggering" Fermi Lab 1994
"SCI Subsystems for HEP Experiments" Open Bus Systems Paris 1994
"Triggering and Data Aquisition for the LHC" Proceedings of the Fifth International Conference on Electronics for Particle Physics. LeCroy Research Systems, New York, May 1995.
Technical Notes and Reports
Measurement of the data rate into a SCI NodeChip. 1995
Measurement of the data rate out of a SCI NodeChip. 1995
Tests using the NodeChip time-outs and the Effect of SCI Resets. 1995
"Manchester SCI Development Card Technical Description" , Manchester HEPP report MAN/HEP/94/7
"Programming the Manchester Daughter Card" 1994
Timing of SCI transactions based on early measurements with the Dolphin NodeChip Card.
"Performance Measurements of the SCI NodeChip" 1996 This paper describes measurements on the maximum rate that a single NodeChip could place data onto the SCI ringlet, and the maximum rate a single NodeChip could accept data from SCI.
Other SCI WWW Servers
- SCIzzL Home Page
- CERN RD24 Project (it was http://www.cern.ch/RD24/)
- Dolphin SCI Home Page
- University of Oslo SCI Home Page
Detailed Project Descriptions
SCI daughter Card using the Dolphin NodeChip
The goal was to provide a simple but comprehensive test-bed for understanding SCI and evaluate SCI's potential for moving data in a Trigger/DAQ environment. The SCI Daughter Card was designed to interface the CMOS NodeChip from Dolphin Interconnect Solutions to a simple synchronous bus called the Dbus. The functional block diagram show the NodeChip with 4 independent FIFOs for outgoing request, incoming response, incoming request and outgoing response, mirroring the internal configuration of the NodeChip to prevent deadlock. The 6 layer board provides a "memory like" synchronous interface to the external host through the Dbus. The Dbus may be 64 or 32 bits wide and provides memory mapped access to the Daughter Card CSR space FIFOs. The logic is synchronous to an external clock on the Dbus with strobes validating both Dbus address and data.
Current Status: Finished and operational since July 1994
SCI-VME interface
The SCI-VME interface shown here allows the SCI Daughter card to be driven from VME. It is based on the a single chip VME interface (Newbridge SCV64 ) which provides both 32 and 64 bit Master/Slave capability to the VME bus. The local bus of the SCV64 is translated to the Dbus of the Daughter Card using simple programmable logic (22V10 PALs/GALs). The interface will operate at local clock speeds up to 25 MHz. This local clock is used for both the local VME interface and the Dbus. The interface also incorporates 32 KB of 30 ns SRAM for testing purposes.
Current Status: Finished and operational since July 1994
SCI-C40 interface based on LSI DBV42/44 board
This interface connects the SCI Daughter card to a C40 DSP situated on a TIM module on a DBV42 or DBV44 VME board from Loughborough Sound Images. The proprietary bus (dBex32), which is similar to the C40's local or global buses, is translated to the Dbus on the SCI Daughter Card. The interface logic uses the dBex32 clock which is half the DSP clock speed, in this case 20 MHz. This clock is further divided to provide a 10 MHz clock for the Dbus.
Current Status: Finished and operational since July 1994
Custom C40 VME board and SCI interface - Joint with Royal Holloway
This PCB interface links the C40 on the custom designed VME card with the SCI NodeChip on the Manchester SCI Daughter Card.
Current Status: Design and prototype finished June 1995, PCB version in preparation (Dec 1995)
SCI-PCI interface
This interface will provide an interconnect between SCI and PCI and is aimed at providing low latency, high bandwidth data movement for Trigger/DAQ applications.
The PC format card connects the Dolphin NodeChip via 4 independent FIFOs to either 32 or 64 bit PCI operating at 33 MHz. All the required data switching is transparent to the user. It supports PCI transactions in PCI configuration and memory spaces. PCI bust read and writes are allowed in memory space, with data transferred on each clock. A programmable interrupt mask allows interrupts to be generated when incoming request or responses are received, when the SCI ring is reset, and when any error condition is detected. The interface may act as a PCI master or slave.
Current Status: Design Finished pcb in preparation Jan 1996
Final Status: PCB used in Demo-B testes at CERN in 1997.
Integration of SCI with the Digital Alpha EB66 and AXPpci33 products.
Both the EB66 evaluation board and the AXPpci33 AT format board products from Digital use the Alpha 21066 chip which has an integral PCI interface as well as a memory controller and primary cache.
Extensive work has been carried out on both board level products to deterimine exactly how the Alpha chip drives the PCI, the cache and memory sub-system, and how it responds to interrupt. Measurements show that data may be transferred over the PCI at over 100 Mbytes/s in burst mode and 33 Mbytes/s under program control.
ATLAS Level 2 trigger Lab tests and Beam Tests in 1994 and 1995.
The SCI interfaces were tested in 1994 in 1, 2, 3, and 4 node ringlets using different CPUs and configurations. A logic analyser was used to assess performance of the SCI Read Selected Byte (RSB), SCI Write Selected Byte (WSB), and SCI Move transactions.
SCI Data Generators
This card will be able to 'pump' large amounts of data into a SCI network and can be used to test SCI networks and components under load conditions. The design will be based on the Link Controller Chips from Dolphin and will be able to send data at a programmed rate or in response to an external trigger.
Current Status: Requirements and design under discussion with CERN and Dolphin.
Enjoy, but the usual disclaimers apply!